| Autor: |
Mookyoung Yoo, Kyeongsik Nam, Gyuri Choi, Sanggyun Kang, Byeongkwan Jin, Hyeoktae Son, Kyounghwan Kim, Hyoungho Ko |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
|
| Zdroj: |
Applied Sciences, Vol 12, Iss 22, p 11651 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2076-3417 |
| DOI: |
10.3390/app122211651 |
| Popis: |
This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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