Vedic division methodology for high-speed very large scale integration applications
| Autor: | Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2014 |
| Předmět: |
very high speed integrated circuits
SPICE CMOS logic circuits dividing circuits size 90 nm digit-recurrence architectures Newton-Raphson architectures Goldschmidt architectures CMOS technology complementary metal oxide semiconductor technology spice spectre stage reduction divider circuitry dynamic power consumption propagation delay Dhvajanka formula ancient Vedic mathematics transistor level implementation high-speed very large scale integration applications Vedic division methodology Engineering (General). Civil engineering (General) TA1-2040 |
| Zdroj: | The Journal of Engineering (2014) |
| Druh dokumentu: | article |
| ISSN: | 2051-3305 |
| DOI: | 10.1049/joe.2013.0213 |
| Popis: | Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 ÷ 16) bit divider circuitry was only ∼300 ns and consumed ∼32.5 mW power for a layout area of 17.39 mm^2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as ∼47, ∼38, 34% reduction in delay and ∼34, ∼21, ∼18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) architectures. |
| Databáze: | Directory of Open Access Journals |
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