Hybrid Digital/Analog Predistorter Architecture With Enhanced Robustness to Hardware Impairments

Autor: Majid Ahmed, Oualid Hammi
Jazyk: angličtina
Rok vydání: 2024
Předmět:
Zdroj: IEEE Access, Vol 12, Pp 113928-113943 (2024)
Druh dokumentu: article
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2024.3443538
Popis: In this paper, a hybrid predistortion architecture that allies the benefits of digital and analog predistortion techniques is investigated. This Hybrid Digital/Analog Predistorter (H-DAPD) uses a low order memory polynomial as a baseband digital predistortion function. To alleviate the complexity of the analog predistorter implementation, an amplitude only predistortion function is adopted. The analog predistortion function is used to perform a coarse linearization of the amplifier. The digital predistortion function is then applied to linearize the system made of the analog predistorter and the power amplifier. The H-DAPD predistortion system is found to be superior to purely analog and to purely digital predistortion systems by combining key advantages present in each of these systems. The robustness of the proposed H-DAPD with respect to the hardware impairments that are typically associated with the implementation of analog predistortion is thoroughly discussed, and shown to be superior to that of conventional hybrid and analog predistortion systems. Experimental validation performed on a commercial power amplifier prototype using 5G new radio (NR) test signals demonstrates the enhanced robustness of the proposed H-DAPD to hardware impairments. It was found that standard compliant adjacent channel leakage ratio is obtained with up to 0.3dB resolution in the analog predistorter’s AM/AM function, and up to 3ns delay misalignment between the input and control signals of the analog predistorter. The proposed system is expected to pave the road for future hybrid predistortion systems.
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