| Autor: |
Jay R. Sheth, Linsheng Zhang, Xiaochuan Shen, Vinay Iyer, Steven M. Bowers |
| Jazyk: |
angličtina |
| Rok vydání: |
2023 |
| Předmět: |
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| Zdroj: |
IEEE Open Journal of the Solid-State Circuits Society, Vol 3, Pp 103-117 (2023) |
| Druh dokumentu: |
article |
| ISSN: |
2644-1349 |
| DOI: |
10.1109/OJSSCS.2023.3290550 |
| Popis: |
This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power $(P_{\mathrm{ out}})$ and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a $1.76\times $ and $1.93\times $ improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average $P_{\mathrm{ out}}$ of 14 dBm with an r.m.s. error vector magnitude $({\mathrm{ EVM}}_{\mathrm{ rms}})$ of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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