A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Autor: Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin
Jazyk: angličtina
Rok vydání: 2021
Předmět:
Zdroj: Sensors, Vol 21, Iss 19, p 6591 (2021)
Druh dokumentu: article
ISSN: 21196591
1424-8220
DOI: 10.3390/s21196591
Popis: An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.
Databáze: Directory of Open Access Journals
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