| Autor: |
S Anto Mamman Shane, J Muralidharan |
| Jazyk: |
English<br />French |
| Rok vydání: |
2023 |
| Předmět: |
|
| Zdroj: |
E3S Web of Conferences, Vol 399, p 01005 (2023) |
| Druh dokumentu: |
article |
| ISSN: |
2267-1242 |
| DOI: |
10.1051/e3sconf/202339901005 |
| Popis: |
A synchronous binary counter is a fundamental component in VLSI design which are used commonly. synchronous binary counter is fast and are used in many applications as it supports wide bit-width. Due to large fan-outs and long carry chains many previous counters have low counting rate when the size of the counters is large. A new fast structure has been suggested for synchronous binary counter with a very low delay for counter with size ranging from 8 to 128 bits. To reduce the complexity of hardware a 1-bit Johnson counter has been used and then duplicate it to minimise propagation delay induced by large fan-outs. The suggested design is realised with a small number of flip-flops, using a back carry propagation counter and a counter based on state look ahead logic, which reduces power and delay. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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