REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM
| Autor: | Butheena R. kadhim, Fatih Korkmaz |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: | |
| Zdroj: | Mağallaẗ Al-kūfaẗ Al-handasiyyaẗ, Vol 13, Iss 1, Pp 82-101 (2022) |
| Druh dokumentu: | article |
| ISSN: | 2071-5528 2523-0018 |
| DOI: | 10.30572/2018/KJE/130105 |
| Popis: | Low-Density Parity-Check (LDPC) code approaches Shannon–limit execution for twofold field and long code lengths. The point of this work is to propose an LDPC calculation for Min Sum (MS) deciphering and playing out its equipment execution investigation inside a proposed communication framework. The MS calculation principally utilizes the base and expansion finding procedure. The quantity of increases is subsequently altogether diminished, which tends to decrease the execution intricacy. The consequences of the reenactment show that the proposed MS interpreting calculation performs the same as the translating of the Sum-Product Algorithm (SPA) while keeping up with the principle highlights of the MS disentangling. The further developing execution by diminishing the number of stages in the deciphering system, diminishing the intricacy of the implementation of the Field Programmable Gate Array (FPGA). |
| Databáze: | Directory of Open Access Journals |
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