A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Autor:	Shi Zuo, Jianzhong Zhao, Yumei Zhou
Jazyk:	angličtina
Rok vydání:	2021
Předmět:	SSPLL hybrid dual path loop low jitter low power consumption Chemical technology TP1-1185
Zdroj:	Sensors, Vol 21, Iss 22, p 7648 (2021)
Druh dokumentu:	article
ISSN:	1424-8220
DOI:	10.3390/s21227648
Popis:	This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.
Databáze:	Directory of Open Access Journals
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