PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation

Autor: José A. Juárez‐Abad, Jorge L. Barahona‐Avalos, Jesús Linares‐Flores
Jazyk: angličtina
Rok vydání: 2021
Předmět:
Zdroj: IET Power Electronics, Vol 14, Iss 8, Pp 1529-1539 (2021)
Druh dokumentu: article
ISSN: 1755-4543
1755-4535
DOI: 10.1049/pel2.12131
Popis: Abstract This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asymmetric Cascade Multilevel Inverter is treated (B‐ACMLI). We employ an FPGA‐based switching‐controller to provide pulses for Multilevel Inverter (MLI) power semiconductors via their gate‐drivers. The modulation strategies were implemented via an FPGA with a 32‐bit floating‐point architecture considering the IEEE‐754 standard's recommendations. The portability of the design is ensured using VHDL . The use of embedded RAM blocks minimizes the logical resources consumed into the FPGA, increases overall speed, and reduces power consumption. A comparison is presented in terms of the number of resources used in both modulation techniques. A low‐cost FPGA board named Pipistrello is used. Pipistrello is an FPGA development board for Xilinx Spartan‐6 LX45, designed by Saanlima Electronics. The platform consisting of a single‐phase seven‐level inverter B‐ACMLI hardware prototype. The experimental results show the effectiveness of the approach. As isolated voltage‐sources, photovoltaic modules are used for the experimental setup to the B‐ACMLI.
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