| Autor: |
Kazuki Tsuda, Kazuma Furutani, Yuto Yakubo, Hiromichi Godo, Yoshinori Ando, Atsutake Kosuge, Toru Nakura, Shunpei Yamazaki |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
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| Zdroj: |
IEEE Journal of the Electron Devices Society, Vol 12, Pp 594-604 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2168-6734 |
| DOI: |
10.1109/JEDS.2024.3439712 |
| Popis: |
We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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