| Autor: |
Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag |
| Jazyk: |
angličtina |
| Rok vydání: |
2019 |
| Předmět: |
|
| Zdroj: |
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 5, Iss 1, Pp 10-18 (2019) |
| Druh dokumentu: |
article |
| ISSN: |
2329-9231 |
| DOI: |
10.1109/JXCDC.2019.2909912 |
| Popis: |
The energy and delay reductions from CMOS scaling have stagnated, motivating the search for a CMOS replacement. Spintronic devices are one of the promising beyond-CMOS alternatives. However, they exhibit high switching error rates of 1% or more when operated at energy and delay comparable to CMOS, rendering them incompatible with the deterministic nature of digital implementations. In this paper, we employ a Shannon-inspired model of computation to enhance the tolerance of all-spin logic (ASL)-based implementations to gate-level switching errors. We develop the logic-level path delay reallocation techniques to shape the output error statistics and propose a novel error compensation scheme to achieve 1000× higher tolerance to device-level switching errors while maintaining the classification accuracy of an ASL-based support vector machine (SVM) classifier. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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