Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded Systems

Autor:	ZAGAN, I., TANASE, C. A., GAITAN, V. G.
Jazyk:	angličtina
Rok vydání:	2020
Předmět:	pipeline processing field programmable gate arrays architecture operating systems scheduling Electrical engineering. Electronics. Nuclear engineering TK1-9971 Computer engineering. Computer hardware TK7885-7895
Zdroj:	Advances in Electrical and Computer Engineering, Vol 20, Iss 1, Pp 63-70 (2020)
Druh dokumentu:	article
ISSN:	1582-7445 1844-7600
DOI:	10.4316/AECE.2020.01009
Popis:	Task context switching, unitary management of events, synchronization and communication mechanisms are significant problems for each real-time operating system. For real-time systems, another overhead factor is the processor's time to execute the routine of treating external asynchronous interrupts. The main objective of this paper is to describe, implement, and validate the preemptive scheduler module as part of the hardware accelerated real-time operating system, using the RISC-V instruction set and Verilog HDL. The new architecture contains the hardware structure used for static and dynamic scheduling of the tasks, real-time management of the events, and also defines a method used to attach interrupts to tasks. In order to accomplish this objective, it was necessary to structure CPU modules so as to ensure easy adaptation to other implementations (MIPS coprocessor, ARM or RISC-V).
Databáze:	Directory of Open Access Journals
Externí odkaz:	https://doaj.org/article/d0074686f8f74e708b17efe389c25ac6 Zobrazit plný text záznamu View record in DOAJ