| Autor: |
Liang, Zehong, Yan, Xiongbo, Ning, Zhe, Hu, Jun, Jiang, Xiaoshan, Sun, Yunhua, Pan, Weiyan, Ye, Jingbo |
| Rok vydání: |
2024 |
| Předmět: |
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| Druh dokumentu: |
Working Paper |
| Popis: |
We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time measurement on 32-channel rising edges and 32-channel falling edges. The average time resolution or the Least Significant Bit (LSB) of the 64 channels is measured to be 3 ps level, with an average root mean square (RMS) precision of 4.77 ps, and a maximum RMS below 8 ps. We also propose an online processing scheme that handles the bubble issues caused by clock region skew. |
| Databáze: |
arXiv |
| Externí odkaz: |
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