From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration
| Autor: | Wu, Heng, Lu, Haoran, Peng, Wanyue, Xu, Ziqiao, Chu, Yanbang, Sun, Jiacheng, Zhou, Falong, Wu, Jack, Zhang, Lijie, Bu, Weihai, Kang, Jin, Li, Ming, Lin, Yibo, Wang, Runsheng, Zhang, Xin, Huang, Ru |
|---|---|
| Rok vydání: | 2024 |
| Předmět: | |
| Zdroj: | Proc. of EDTM 2025 |
| Druh dokumentu: | Working Paper |
| Popis: | In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones. Comment: Accepted by EDTM 2025 |
| Databáze: | arXiv |
| Externí odkaz: |
|