Hypervisor Extension for a RISC-V Processor

Autor:	Gauchola, Jaume, Costa, JuanJosé, Morancho, Enric, Canal, Ramon, Carril, Xavier, Doblas, Max, Otero, Beatriz, Pajuelo, Alex, Rodríguez, Eva, Salamero, Javier, Verdú, Javier
Rok vydání:	2024
Předmět:	Computer Science - Hardware Architecture
Druh dokumentu:	Working Paper
Popis:	This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one. Comment: RISC-V Summit Europe 2023, June 5-9, 2023
Databáze:	arXiv
Externí odkaz:	http://arxiv.org/abs/2406.17796 Zobrazit plný text záznamu View this record from Arxiv