Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
| Autor: | Hu, Tao, Shao, Xianzhou, Bai, Mingkai, Jia, Xinpei, Dai, Saifei, Sun, Xiaoqing, Han, Runhao, Yang, Jia, Ke, Xiaoyu, Tian, Fengbin, Yang, Shuai, Chai, Junshuai, Xu, Hao, Wang, Xiaolei, Wang, Wenwu, Ye, Tianchun |
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| Rok vydání: | 2024 |
| Předmět: | |
| Druh dokumentu: | Working Paper |
| Popis: | We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET. Comment: 6 pages, 12 figures. arXiv admin note: substantial text overlap with arXiv:2404.15825 |
| Databáze: | arXiv |
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