Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization

Autor:	Lu, Yao, Zhang, Jide, Zheng, Su, Li, Zhen, Wang, Lingli
Rok vydání:	2022
Předmět:	Computer Science - Hardware Architecture Computer Science - Machine Learning
Druh dokumentu:	Working Paper
DOI:	10.1109/ISCAS48785.2022.9937665
Popis:	In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset. Comment: ISCAS 2022. 5pages, 1 figure
Databáze:	arXiv
Externí odkaz:	http://arxiv.org/abs/2210.03916 Zobrazit plný text záznamu View this record from Arxiv