Development of a new high-speed data acquisition system prototype for SOI pixel detector using SiTCP-XG, a 10-gigabit Ethernet network processor
| Autor: | Nishimura, Ryutaro, Kishimoto, Shunji, Arai, Yasuo, Miyoshi, Toshinobu |
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| Rok vydání: | 2022 |
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| Zdroj: | 2022 J. Phys.: Conf. Ser. 2374 012093 |
| Druh dokumentu: | Working Paper |
| DOI: | 10.1088/1742-6596/2374/1/012093 |
| Popis: | We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit Ethernet. In this new readout board, the SiTCP-XG network processor supporting 10-gigabit Ethernet was implemented. SiTCP is a network processor circuit running on FPGA, and SiTCP-XG is the newly developed version of the SiTCP that supports 10-gigabit Ethernet. Before developing the new board, we constructed a prototype system using the Xilinx FPGA evaluation board KC705 to evaluate the SiTCP-XG. This prototype system was tested with the SOI pixel detector, which has 425,984 (column 832 x row 512 matrix) pixels and a pixel size of 17 x 17 um at the synchrotron beamlines of the PhotonFactory (KEK). This was the first test of the X-ray imaging for this system. The results showed that this system worked stably with a transfer rate of 682 Mbps (equivalent to a frame rate of 100 fps, limited by detector operation parameters), and also worked stably with a transfer rate of 2.4 Gbps (equivalent to 350 fps, the maximum rate limited by the detector performance). These results suggest that the SiTCP-XG system has sufficient transfer performance to cover the SOIPIX detector performance. Comment: Accepted for publication in the proceedings of the International Conference on Technology and Instrumentation in Particle Physics 2021 (TIPP2021, 24-28 May 2021), to be published in Journal of Physics: Conference Series |
| Databáze: | arXiv |
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