| Autor: |
Milutinovic, Veljko, Azer, Erfan Sadeqi, Yoshimoto, Kristy, Klimeck, Gerhard, Djordjevic, Miljan, Kotlar, Milos, Bojovic, Miroslav, Miladinovic, Bozidar, Korolija, Nenad, Stankovic, Stevan, Filipović, Nenad, Babovic, Zoran, Kosanic, Miroslav, Tsuda, Akira, Valero, Mateo, De Santo, Massimo, Neuhold, Erich, Skoručak, Jelena, Dipietro, Laura, Ratkovic, Ivan |
| Rok vydání: |
2020 |
| Předmět: |
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| Druh dokumentu: |
Working Paper |
| Popis: |
This article starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used Machine Learning algorithms needed in bandwidth-bound applications and a flexible-structure reprogrammable accelerator for less frequently used Machine Learning algorithms needed in latency-critical applications. |
| Databáze: |
arXiv |
| Externí odkaz: |
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