Analysis and validation of low-frequency noise reduction in MOSFET circuits using variable duty cycle switched biasing
| Autor: | Jainwal, Kapil, Sarkar, Mukul, Shah, Kushal |
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| Rok vydání: | 2017 |
| Předmět: | |
| Druh dokumentu: | Working Paper |
| Popis: | Randomization of the trap state of defects present at the gate Si-SiO$_2$ interface of MOSFET is responsible for the low-frequency noise phenomena such as Random Telegraph Signal (RTS), burst, and 1/\textit{f} noise. In a previous work, theoretical modelling and analysis of the RTS noise in MOS transistor was presented and it was shown that this 1/\textit{f} noise can be reduced by decreasing the duty cycle ($f_{D}$) of switched biasing signal. In this paper, an extended analysis of this 1/\textit{f} noise reduction model is presented and it is shown that the RTS noise reduction is accompanied with shift in the corner frequency ($f_{c}$) of the 1/\textit{f} noise and the value of shift is a function of continuous ON time ({$T_{on}$}) of the device. This 1/\textit{f} noise reduction is also experimentally demonstrated in this paper using a circuit configuration with multiple identical transistor stages which produces a continuous output instead of a discrete signal. The circuit is implemented in 180~nm standard CMOS technology, from UMC. According to the measurement results, the proposed technique reduces the 1/\textit{f} noise by approximately 5.9 dB at $f_{s}$ of 1~KHz for 2 stage, which is extended up to 16 dB at $f_{s}$ of 5 MHz for 6 stage configuration. Comment: 16 pages, 13 figures |
| Databáze: | arXiv |
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