Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology
Autor: | Chaudhuri, Sumanta, Graba, Tarik, Mathieu, Yves |
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Rok vydání: | 2016 |
Předmět: | |
Druh dokumentu: | Working Paper |
Popis: | In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks. Comment: The paper contains anonymous reviews at the end. 11 pages |
Databáze: | arXiv |
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