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This thesis describes the integration of a RISC core processor with the MIPS assembly language. The COFFEE Core is a RISC core processor developed at Tampere University of Technology. The compiler and tools, based on GCC and GNU Binutils, are several versions behind the current releases. To become more widely adopted in research and industry, the processor would need to use up-to-date industry standard tools. Modifying the processor to use the MIPS or ARM instruction set would allow the associated tools to be used as well. The COFFEE architecture is compared with both the MIPS and ARM architectures to determine which architecture would provide the most benefits to developers and how the COFFEE Core might be adapted to meet the architectural requirements. When compared with the COFFEE instruction set, the ARM instruction set is found to have an overlap of 7 identical instructions and 32 similar instructions and the MIPS instruction set is found to have an overlap of 22 identical instructions and 54 similar instructions. MIPS and ARM were also found to be comparably beneficial to developers. After these comparisons, the MIPS architecture was selected as the most compatible, due to the larger overlap in the instruction set compared to ARM. A subset of overlapping MIPS instructions was chosen to be mapped to the corresponding COFFEE instructions. The Decoder and Control Unit of the COFFEE Core was modified and the processor was tested with MIPS assembly, finding the implemented instructions to be functional. The integration of MIPS with the COFFEE Core is therefore shown to be feasible. Additional modifications outside the Decoder and Control Unit of the COFFEE Core would be required to implement the remaining MIPS instructions. |
