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In this thesis, a system to wirelessly synchronize clock signals within multiple spatially distributed stations, is developed. The local clock signals of the stations are derived from quartz crystal oscillators and thus show a frequency mismatch. These local clocks get synchronized to a master clock which is spatially separated from the slave clocks. The concept is based on the operational principle of a standard phase locked loop (PLL) but is expanded to support the realization with a standard micro controller unit (MCU) like the STM32H743. Since most of the tasks are not realized in discrete hardware components but in software, the expanded concept is referred to as software phase locked loop (SPLL). A master station defines its local signal as the reference clock and distributes this signal via a Texas Instruments CC1101 433MHz radio frequency (RF) link to any number of slave stations. The input capture (IPC) unit of the MCU is used to determine the phase deviation between the local slave clock and the master reference clock. Special focus is put on this estimation process as the RF-link transmission results in a very noisy signal detected by the slaves. A study of the dynamics of the operational frequency drift of the quartz crystal oscillator provides the needed insights to separate the contributions within the superposition of the phase drift between the stations and the noise introduced by the transmission. In addition to the noise within the reference signal, the system needs to detect transmission errors within the signal, in order to minimize the variance of the resulting phase deviation estimation. To do so the operational principle of the SPLL provides a very useful setup, since the disrupted reference signal is compared to the nearly identical local slave signal which is not being influenced by transmission errors. Once the phase deviation is determined a PID-control algorithm is used to calculate an appropriate frequency adjustment of the local slave clock. This adjustment of the operational frequency of the slave is implemented within the frequency synthesizer stage of a SiLabs Si5341 clock generator chip. The Si5341 provides the ability to change the value of its internal fractional frequency divider in very small incremental steps, at a repetition speed of 1 MHz. This frequency-adjusted signal is the feedback signal used to determine the phase deviation to the master reference signal. Thus, finally a closed-loop system is established. The performance of the system is evaluated based on three metrics. The stability of the synchronized SPLL output clock frequency is analyzed with the Allan variance. It provides a measure of the dominant noise processes by comparing the clock under test to a far more accurate reference clock. To analyze the synchronicity between the stations their instantaneous frequency ratios are measured. The final criterion is the determination of the time deviation between the synchronized stations. The system is capable of keeping the standard deviation of this time deviation in the single-digit nanosecond range. submitted by Martin Friedl BSc Universität Linz, Masterarbeit, 2021 (VLID)5795524 |
