Architecture of an integrated microelectronic warfare system on a chip and design of key components
| Autor: | Luke, Brian L. |
|---|---|
| Přispěvatelé: | Fouts, Douglas J., Pace, Phillip E., Naval Postgraduate School (U.S.) |
| Rok vydání: | 2004 |
| Předmět: |
dynamic range
electronic warfare counterflow clock pipeline inverse synthetic aperture radar automatic clock skew control robust sym-metric number system digital image synthesis anti-ship ca-pable missile radar countermeasures Folding ADC system-on-a-chip residue number system wideband imaging radar Electronics in military engineering gray-code properties |
| Popis: | This dissertation investigates a mixed-signal, electronic warfare (EW) system-on-a-chip (SoC) design capable of synthesizing false radar returns in response to imaging radar interrogations that, when integrated into the range-Doppler processing, form an image of a false target. Detailed designs for the EW SoC components including the false target digital image synthesizer (DIS) and a novel analog to digital converter (ADC) are provided in this research. Alternative DIS architectures are presented that reduce circuit die area and power dissipation. This research also describes the theory, design, implementation, simulation, and testing of a proof-of-concept application-specific integrated circuit (ASIC) providing automatic counterflow-clock pipeline skew control for the DIS. High performance ADCs are key components of mixed-signal SoCs. Design and simulation results for an 8-bit 1 GS/s robust symmetric number system (RSNS) folding ADC are presented. The gray-code properties of the RSNS make it desirable for error control and low-power ADC implementations. A complete mathematical description of the N-modulus RSNS redundancies is discovered, which results in closed-form expressions for the longest sequence of unique RSNS vectors for moduli of the form m - 1, m, and m +1, as well as an efficient search algorithm for N-modulus systems at least six orders of magnitude faster than previously published results. Lastly, an N-modulus RSNS-to-binary converter design procedure and a circuit design for an 8-bit, 4-modulus 1 GS/s RSNS-to-binary converter are presented. http://archive.org/details/architectureofni109459908 Approved for public release; distribution is unlimited. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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