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Targeting to improving the efficiency of real-time Fourier Transform computations with large input data sets, this paper presents the design and the VLSI implementation of 16K, 64K and 265K complex points Fast Fourier Transform (FFT) systolic architectures. These organizations are deeply pipelined to maximize the operating frequency and follow the approach of decomposing the transforms into 64-point FFT computations to minimize the buffer size between consecutive stages. The resulting organizations achieve real time performance on testing and observation applications. They include simple processing elements and they are scalable with respect to the operating frequency and data width. Validation on FPGA showed operation at 250MHz and 125MHz for the 16K and the 64K architectures with throughput 1Gs/s and 500Ms/s respectively. The VLSI implementations of the proposed 16K, 64K and 265K architectures achieve post-route clock frequencies of 352, 256.5, and 188 MHz respectively and they can sustain throughputs of 1.4Gs/s, 1Gs/s and 188Ms/s. |
