| Autor: |
Tuyaerts, Romain, van Overmeere, Quentin, Favache, A., Whyte Ferreira, Clara, Scheen, Gilles, Raskin, Jean-Pierre |
| Přispěvatelé: |
UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Popis: |
In a previous study, we presented a porosification method of a heavily-doped silicon substrate in post-process CMOS fabrication to overcome the compatibility issues relative to the introduction of porous silicon into a CMOS process flow. After microelectronic circuits fabrication on the top layer of the substrate, the handle silicon substrate is porosified via the backside. The biasing of the substrate is done on the periphery of the backside to avoid the involvement of the electronic circuits on the frontside. Since that former demonstrator requires a heavily-doped starting silicon substrate which could be a source of contamination for fab production line, in this study, we present an alternative post-process CMOS and backside porosification applied to a standard resistivity silicon substrate. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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