| Autor: |
Simon, William Andrew, Galicia, Juan-Martin, Levisse, Alexandre Sébastien Julien, Zapater Sancho, Marina, Atienza Alonso, David |
| Předmět: |
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| Popis: |
In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4/1.5Ghz for 32/64bit additions respectively), reliable (no read disturb issues) and wide voltage range (from 0.6 to 1V) 6T SRAM-based IMC architecture using local bitlines and a fast carry adder pitched below the memory subarray. We verify the proposed architecture through layout and variability aware simulations in 28nm bulk high performances technology PDK. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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