A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications
| Autor: | Zong, Z., Chen, Peng, Staszewski, R.B. |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Fractional-N PLL
Phase noise (PN) Flicker noise Harmonic extraction Mm-wave (mmW) Harmonic boosting Flicker noise upconversion Time-to-digital converter (TDC) 60 GHz Digital-to-time converter (DTC) Fractional spur suppression Digitally controlled oscillator (DCO) Hardware_INTEGRATEDCIRCUITS Implicit multiplier All-digital phase-locked loop (ADPLL) |
| Zdroj: | IEEE Journal of Solid State Circuits, 54(3) |
| ISSN: | 0018-9200 |
| Popis: | In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3 ) and thermal (1/f 2 ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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