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In this work a diversification of adding methods including the engrossing of the proposed Fin-Field Effect Transistor technology, are analyzed. A variety of different Complementary Metal Oxide Semiconductor Full Adder reconstruction approaches have been analyzed for area, run time, potential and figure of merit. Study of facts has been examined for conventional circuits. Hypothetically sophisticated Fin-Field Effect Transistor Gate Diffusion Input adder, designed framework principles antiquated outstandingly improved the structure of full adder in contrast with the conventional methods. In this technique the Fin-Field Effect Transistor technology achieves 90%reduction of chip area, power is abated by 73% and run time is reduced compared to the referred full adder circuits. Synthesis results of proposed adder have been employed with the help of cadence Electronic Design Automation tool. The Proposed Fin-Field Effect Transistor Gate Diffusion Input adder leads to high performance, low path delay and reduce lack of synchronization |
