Test set compaction for combinational circuits
| Autor: | Jau-Shien Chang, Chen-Shang Lin |
|---|---|
| Rok vydání: | 2003 |
| Předmět: |
Combinational logic
Engineering business.industry Compaction Automatic test pattern generation Fault (power engineering) Computer Graphics and Computer-Aided Design Upper and lower bounds Fault detection and isolation Robustness (computer science) Test set Fault coverage Benchmark (computing) Electronic engineering Pruning (decision trees) Electrical and Electronic Engineering business Test size Algorithm Software Test set compaction |
| Zdroj: | Proceedings First Asian Test Symposium (ATS `92). |
| DOI: | 10.1109/ats.1992.224429 |
| Popis: | Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST. > |
| Databáze: | OpenAIRE |
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