BYOC: A 'bring your own core' framework for heterogeneous-ISA research
| Autor: | Ang Li, Yaosheng Fu, Katie Lim, Grigory Chirkov, Alexey Lavrov, Florian Zaruba, Michael Schaffner, Tri Nguyen, Kunal Gulati, Fei Gao, Luca Benini, David Wentzlaff, Jonathan Balkind |
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| Přispěvatelé: | Balkind J., Lim K., Schaffner M., Gao F., Chirkov G., Li A., Lavrov A., Nguyen T.M., Fu Y., Zaruba F., Gulati K., Benini L., Wentzlaff D. |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Computer science
Interface (computing) Research platform Heterogeneous-ISA Manycore Architecture Open source RISC-V x86 SPARC X86 02 engineering and technology computer.software_genre 01 natural sciences 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Field-programmable gate array 010302 applied physics 020202 computer hardware & architecture Computer architecture Scalability Compiler computer Cache coherence System software |
| Zdroj: | ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS |
| Popis: | Heterogeneous architectures and heterogeneous-ISA designs are growing areas of computer architecture and system software research. Unfortunately, this line of research is significantly hindered by the lack of experimental systems and modifiable hardware frameworks. This work proposes BYOC, a "Bring Your Own Core" framework that is specifically designed to enable heterogeneous-ISA and heterogeneous system research. BYOC is an open-source hardware framework that provides a scalable cache coherence system, that includes out-of-the-box support for four different ISAs (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9) and has been connected to ten different cores. The framework also supports multiple loosely coupled accelerators and is a fully working system supporting SMP Linux. The Transaction-Response Interface (TRI) introduced with BYOC has been specifically designed to make it easy to add in new cores with new ISAs and memory interfaces. This work demonstrates multiple multi-ISA designs running on FPGA and characterises the communication costs. This work describes many of the architectural design trade-offs for building such a flexible system. BYOC is well suited to be the premiere platform for heterogeneous-ISA architecture, system software, and compiler research. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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