Hardware implementation of 1-D 8-point adaptive multiple transform in post-HEVC standard

Autor: Ahmed Kammoun, Sonda Ben Jdidia, Nouri Masmoudi, Fatma Belghith
Přispěvatelé: Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'électronique et des technologies de l'Information [Sfax] (LETI), École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)
Jazyk: angličtina
Rok vydání: 2017
Předmět:
Zdroj: 2017 18th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)
2017 18th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), Dec 2017, Monastir, France. pp.146-151
Popis: Despite the coding efficiency improvement cognized per HEVC standard, researchers are still devoting so much efforts for further enhancements. The latest result of ITU-T and ISO/IEC collaboration was the definition of a new standardization initiative beyond HEVC which is POST-HEVC standard. It is actually under development and scheduled to be completed in 2020. It offers many contributions specifically in the transform module. In fact, it has introduced a new approach called Adaptive Multiple Transform (AMT) which raises the issue of additional computational complexity. This work proposes hardware architectures of the 1-D 8-point Adaptive Multiple Transform for all transform types. This theme is innovative since it was not dealt with before. In this paper two transform implementations aspects are detailed and compared. The first method is based on using Altera multipliers (LPM) and the second one exploits correlation and symmetry properties in order to reduce matrix multiplications complexity. The adopted method was implemented in VHDL and it is capable to process at 288 MHZ under a Stratix III device. The number of execution cycles of this architecture can reach a maximum of 12 cycles when 8-point-1D-DCT-VIII is computed.
Databáze: OpenAIRE