Mixed Criticality Systems with Varying Context Switch Costs
| Autor: | Davis, R.I., Altmeyer, S., Burns, A., Pellizzoni, R. |
|---|---|
| Přispěvatelé: | System and Network Engineering (IVI, FNWI) |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Mixed criticality
Correctness Computer science Distributed computing Preemption 020207 software engineering 02 engineering and technology 020202 computer hardware & architecture Scheduling (computing) Memory address Criticality 0202 electrical engineering electronic engineering information engineering Cache ddc:004 Context switch |
| Zdroj: | RTAS 2018: 24th IEEE Real-Time and Embedded Technology and Applications Symposium : proceedings : 11-13 April 2018, Porto, Portugal, 140-151 STARTPAGE=140;ENDPAGE=151;TITLE=RTAS 2018 RTAS |
| Popis: | In mixed criticality systems, it is vital to ensure that there is sufficient separation between tasks of LO- and HI-criticality applications, so that the behavior or mis-behavior of the former cannot affect the functional or timing correctness of the latter. To ensure appropriate spatial isolation, the memory address spaces and cache use by LO- and HI-criticality tasks must be distinct. A consequence of this separation is that the cost of switching between tasks of the same criticality can be small, whereas the cost of context switching between tasks of different criticality levels can be much larger. In this paper, we focus on integrating the differing context switch costs into fixed priority preemptive scheduling, and the two mixed criticality scheduling schemes based on it: SMC and AMC. We derive simple, refined, and multi-set analyses for each scheme. Further, we show that the refined and multi-set analyses are not compatible with Audsley's Optimal Priority Assignment algorithm, we therefore propose a heuristic priority assignment policy aimed at reducing the number of high cost context switches. Our evaluation is grounded in measurements of context switch times (save and restore costs) from a prototype implementation of an explicitly managed cache on an FPGA. The evaluation shows the effectiveness of the derived analyses and the proposed priority assignment policy. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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