Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

Autor:	Eduardo Peralias, Antonio Gines, Adoración Rueda, Juan Núñez
Přispěvatelé:	Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Gobierno de España, European Space Agency (ESA)
Rok vydání:	2016
Předmět:	Engineering Design space exploration Pipeline (computing) Ultra-low jitter High-speed high-resolution ADCs Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology law.invention law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Clock recovery Pipeline ADCs Electronic circuit Jitter business.industry 020208 electrical & electronic engineering Transistor 020202 computer hardware & architecture Surfaces Coatings and Films CMOS Hardware and Architecture Design methodology Signal Processing business Voltage
Zdroj:	idUS. Depósito de Investigación de la Universidad de Sevilla instname Digital.CSIC. Repositorio Institucional del CSIC
ISSN:	1573-1979 0925-1030
Popis:	This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fb6cd836a4004082f4c99b32c16453f1 https://doi.org/10.1007/s10470-016-0870-6 Zobrazit plný text záznamu Full text from SpringerLink