A low-cost susceptibility analysis methodology to selectively harden logic circuits
| Autor: | Alberto Bosio, B. Deveautour, Patrick Girard, Imran Wali, M. Sonza Reorda, Arnaud Virazel |
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| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Computer science Design space exploration Fault tolerance Electrical element 02 engineering and technology Fault injection 01 natural sciences 020202 computer hardware & architecture Reliability engineering Fault tolerant architecture Stuck-at fault Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Estimation methods |
| Zdroj: | ETS |
| Popis: | Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with design complexity. In this paper we introduce a low-cost susceptibility analysis methodology that helps identifying the most vulnerable circuit elements for hardening with less computational effort and orders of magnitude faster. Our experimental results show that the methodology offers huge gain in terms of computational effort (2,500× faster) in comparison with a fault-injection based method and produces results within acceptable degree of accuracy. |
| Databáze: | OpenAIRE |
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