Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

Autor:	Stefan Kubicek, G. Raskin, B. De Jaeger, M.M. Heyns, Ben Kaczer, Thomas Chiarella, Thierry Conard, Ivo Teerlinck, Sun-Ghil Lee, Matty Caymax, Alessandra Satta, Valery V. Afanas'ev, K. De Meyer, J. Van Steenbergen, J. Poortmans, P. Mijlemans, Serge Biesemans, Wilfried Vandervorst, Paul W. Mertens, Marc Schaekers, Robin Degraeve, Lars-Ake Ragnarsson, Eddy Kunnen, JL Autran, Tom Schram, Erik Sleeckx, S. Van Elshocht, Annelies Delabie, M. Meuris, Michel Houssa, Richard Lindsay, G. Kota, Werner Boullart, J. Croon, E. Van Moorhem, Gillis Winderickx, Andre Stesmans, Peter Verheyen
Rok vydání:	2004
Předmět:	Materials science business.industry Physics Gate dielectric Dielectric Atomic layer deposition Gate oxide MOSFET Electronic engineering Optoelectronics business Metal gate High-κ dielectric Leakage (electronics)
Zdroj:	Scopus-Elsevier 34th European Solid-State Device Research Conference (ESSDERC 2004), SEP 21-23, 2004, Leuven, BELGIUM ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE
DOI:	10.1109/essder.2004.1356521
Popis:	We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f95367a37842fb87890d460112e6d35d https://doi.org/10.1109/essder.2004.1356521 Zobrazit plný text záznamu