RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
| Autor: | Hiromu Miyazaki, Kenji Kise, Ashraful Islam, Takuto Kanamori |
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| Rok vydání: | 2020 |
| Předmět: |
FOS: Computer and information sciences
Instructions per cycle Computer science Pipeline (computing) 02 engineering and technology Instruction set C.1.1 Artificial Intelligence Hardware Architecture (cs.AR) Data structure alignment 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering Computer Science - Hardware Architecture Field-programmable gate array computer.programming_language business.industry Fetch 020206 networking & telecommunications Branch predictor Hardware and Architecture Embedded system RISC-V Verilog 020201 artificial intelligence & image processing Computer Vision and Pattern Recognition business computer Software Integer (computer science) |
| Zdroj: | IEICE Transactions on Information and Systems. :2494-2503 |
| ISSN: | 1745-1361 0916-8532 |
| DOI: | 10.1587/transinf.2020pap0015 |
| Popis: | RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization including pipelined branch prediction mechanism, ALU optimization, and data alignment and sign-extension optimization for data memory output. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works. 9 pages, 9 figures, this paper is submitted to the Institute of Electronics, Information and Communication Engineers (IEICE) |
| Databáze: | OpenAIRE |
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