Dopant Network Processing Units: Towards Efficient Neural-network Emulators with High-capacity Nanoelectronic Nodes
| Autor: | Hans-Christian Ruiz, Unai Alegre Ibarra, Wilfred G. van der Wiel, Hajo Broersma, Bram van de Ven, PA Peter Bobbert |
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| Přispěvatelé: | Nano Electronics, MESA+ Institute, Digital Society Institute, Formal Methods and Tools |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
FOS: Computer and information sciences
Computer Science - Machine Learning Artificial neural network Computer science Information processing Computer Science - Emerging Technologies Computer Science - Neural and Evolutionary Computing Machine Learning (stat.ML) Energy consumption Memristor Machine Learning (cs.LG) law.invention Emerging Technologies (cs.ET) Binary classification Computer engineering law Statistics - Machine Learning Hardware Architecture (cs.AR) Neural and Evolutionary Computing (cs.NE) Latency (engineering) Computer Science - Hardware Architecture Throughput (business) MNIST database |
| Zdroj: | Neuromorphic Computing and Engineering, 1(2):024002. Institute of Physics Publishing |
| ISSN: | 2634-4386 |
| Popis: | The rapidly growing computational demands of deep neural networks require novel hardware designs. Recently, tunable nanoelectronic devices were developed based on hopping electrons through a network of dopant atoms in silicon. These "Dopant Network Processing Units" (DNPUs) are highly energy-efficient and have potentially very high throughput. By adapting the control voltages applied to its terminals, a single DNPU can solve a variety of linearly non-separable classification problems. However, using a single device has limitations due to the implicit single-node architecture. This paper presents a promising novel approach to neural information processing by introducing DNPUs as high-capacity neurons and moving from a single to a multi-neuron framework. By implementing and testing a small multi-DNPU classifier in hardware, we show that feed-forward DNPU networks improve the performance of a single DNPU from 77% to 94% test accuracy on a binary classification task with concentric classes on a plane. Furthermore, motivated by the integration of DNPUs with memristor arrays, we study the potential of using DNPUs in combination with linear layers. We show by simulation that a single-layer MNIST classifier with only 10 DNPUs achieves over 96% test accuracy. Our results pave the road towards hardware neural-network emulators that offer atomic-scale information processing with low latency and energy consumption. Minor change: replaced the DNPU on Fig. 1 with a clearer schematic |
| Databáze: | OpenAIRE |
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