Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor
| Autor: | Marek Patyra, Rupesh S. Shelar |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Very-large-scale integration
Engineering Computer science business.industry Microprocessor design CAD Dissipation Computer Graphics and Computer-Aided Design Integrated circuit layout Reliability engineering Glitch Power (physics) law.invention Cycle time Microprocessor law Embedded system Path (graph theory) Datapath Hardware_INTEGRATEDCIRCUITS Electronic engineering Physical design Electrical and Electronic Engineering business Software |
| Zdroj: | ISPD |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2013.2266404 |
| Popis: | In nanometer technologies, even local interconnects are believed to cause major impact on timing, power, repeaters, and routability in VLSI circuits. Although empirical studies exist, there is little comprehensive work that explores the impact of local interconnects on both timing and power in a real high performance microprocessor design in a quantitative manner. To address the void, this article presents results from the extensive study carried out on RTL-to-layout synthesized (RLS) and semi-manually designed structured data path (SDP) blocks in a 45 nm technology microprocessor core. The study shows that for synthesized blocks local interconnects contribute $1/3rd to the worst internal timing paths, on average; in case of datapath blocks, the same contribution is $1/5th. Moreover, regardless of the design style, the interconnects contribute to more than 30% to the dynamic/glitch power. This points to severity of impact due to local interconnects in today's high performance designs and implies that algorithms/approaches underlying existing synthesis/physical design tools/methodologies have limited success in mitigating the same. |
| Databáze: | OpenAIRE |
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