First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip
| Autor: | Nader Bagherzadeh, Nacer-Eddine Zergainoh, Masoumeh Ebrahimi, Alexandre Siqueira Guedes Coelho, Amir Charif |
|---|---|
| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Royal Institute of Technology [Stockholm] (KTH ), Department of Electrical Engineering and Computer Sciences (Berkeley EECS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), University of Turku, University of California [Irvine] (UC Irvine), University of California (UC) |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Computer science Distributed computing Topology (electrical circuits) 02 engineering and technology Adaptive routing Network topology 01 natural sciences Theoretical Computer Science 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS [INFO]Computer Science [cs] Networks on chip network-on-chip 010302 applied physics ta113 Network packet TSV 020202 computer hardware & architecture PACS 8542 Computational Theory and Mathematics Hardware and Architecture adaptative Routing (electronic design automation) Software 3D |
| Zdroj: | IEEE Transactions on Computers IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2018, 67 (10), pp.1430-1444. ⟨10.1109/TC.2018.2822269⟩ IEEE Transactions on Computers, 2018, 67 (10), pp.1430-1444. ⟨10.1109/TC.2018.2822269⟩ |
| ISSN: | 0018-9340 |
| Popis: | International audience; 3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shown to dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. A comprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects to existing solutions. |
| Databáze: | OpenAIRE |
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