High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration
| Autor: | J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup |
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| Přispěvatelé: | Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Materials science
Fabrication business.industry 020208 electrical & electronic engineering Doping Recrystallization (metallurgy) 02 engineering and technology Epitaxy Logic gate 0202 electrical engineering electronic engineering information engineering Optoelectronics 020201 artificial intelligence & image processing [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business |
| Zdroj: | 2017 IEDM Technical Digest 2017 IEEE International Electron Devices Meeting (IEDM) 2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. pp.32.2.1-32.2.4, ⟨10.1109/IEDM.2017.8268484⟩ |
| Popis: | session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration. |
| Databáze: | OpenAIRE |
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