On Preventing SAT Attack with Decoy Key-Inputs

Autor: Sophie Dupuis, Marie-Lise Flottes, Bruno Rouzeyre, Quang-Linh Nguyen
Přispěvatelé: TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
Jazyk: angličtina
Rok vydání: 2021
Předmět:
Zdroj: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021)
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021), Jul 2021, Tampa, United States. pp.114-119, ⟨10.1109/ISVLSI51109.2021.00031⟩
ISVLSI
DOI: 10.1109/ISVLSI51109.2021.00031⟩
Popis: International audience; The globalized supply chain in the semiconductor industry raises several security concerns such as IC overproduction, intellectual property piracy and design tampering. Logic locking has emerged as a Design-for-Trust countermeasure to address these issues. Original logic locking proposals provide a high degree of output corruption-i.e., errors on circuit outputsunless it is unlocked with the correct key. This is a prerequisite for making a manufactured circuit unusable without the designer's intervention. Since the introduction of SAT-based attacks-highly efficient attacks for retrieving the correct key from an oracle and the corresponding locked design-resulting design-based countermeasures have compromised output corruption for the benefit of better resilience against such attacks. Our proposed logic locking scheme, referred to as SKG-Lock, aims to thwart SAT-based attacks while maintaining significant output corruption. The proposed provable SAT-resilience scheme is based on the novel concept of decoy key-inputs. Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks.
Databáze: OpenAIRE