Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments
| Autor: | Guillermo Paya-Vaya, Holger Blume, Tobias Stuckenberg, Pekka Jääskeläinen, Sven Gesper, Stephan Nolting, Moritz Weisbrich |
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| Přispěvatelé: | Tampere University, Computing Sciences, Research area: Computer engineering |
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
business.industry Computer science Design space exploration 02 engineering and technology Type (model theory) Transport triggered architecture 113 Computer and information sciences 01 natural sciences 020202 computer hardware & architecture Microarchitecture Microcontroller Application-specific integrated circuit Very long instruction word 0103 physical sciences 0202 electrical engineering electronic engineering information engineering business Encoder Computer hardware |
| Zdroj: | Lecture Notes in Computer Science ISBN: 9783030275617 SAMOS Lecture Notes in Computer Science Lecture Notes in Computer Science-Embedded Computer Systems: Architectures, Modeling, and Simulation Embedded Computer Systems: Architectures, Modeling, and Simulation-19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings |
| ISSN: | 0302-9743 1611-3349 |
| Popis: | Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system’s performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic,..), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a 0.18µm SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x. acceptedVersion |
| Databáze: | OpenAIRE |
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