Technology independent ASIC based time to digital converter
| Autor: | Alvaro Geraldes, F. S. Alves, Jorge Cabral, Rui Machado |
|---|---|
| Přispěvatelé: | Universidade do Minho |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Ciências Agrárias::Biotecnologia Agrária e Alimentar
Biotecnologia Agrária e Alimentar [Ciências Agrárias] General Computer Science Computer science Thermometers Decoding Design flow Ciência Animal e dos Laticínios [Ciências Agrárias] 02 engineering and technology 01 natural sciences Time interval measurement 010309 optics Time-to-digital converter Software portability Least significant bit Application-specific integrated circuit 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS General Materials Science Field-programmable gate array Ciências Agrárias::Ciência Animal e dos Laticínios computer.programming_language Clocks Science & Technology business.industry 020208 electrical & electronic engineering Hardware description language time interval measurement Application specific integrated circuits General Engineering Linearity Registers Field programmable gate arrays Time-to-digital converter (TDC) Ciências Veterinárias [Ciências Agrárias] time-to-digital converter (TDC) Structured data path (SDP) structured data path (SDP) lcsh:Electrical engineering. Electronics. Nuclear engineering Routing (electronic design automation) business Cmos process computer lcsh:TK1-9971 Application specific integrated circuit (ASIC) Computer hardware Ciências Agrárias::Ciências Veterinárias |
| Zdroj: | Repositório Científico de Acesso Aberto de Portugal Repositório Científico de Acesso Aberto de Portugal (RCAAP) instacron:RCAAP IEEE Access, Vol 8, Pp 195820-195831 (2020) |
| Popis: | This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL’s steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied. (037902) |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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