A Physical Synthesis Flow for Early Technology Evaluation of Silicon Nanowire based Reconfigurable FETs
| Autor: | Dennis Walter, Walter M. Weber, Shubham Rai, Andre Heinzig, Ansh Rupani, Michael Raitza, Christian Mayr, Tim Baldauf, Jens Trommer, Akash Kumar |
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| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Silicon
Computer science ddc:621.3 Design flow chemistry.chemical_element 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY 01 natural sciences Domain (software engineering) law.invention logische Gatter Layout Transistoren Silizium mathematisches Modell Werkzeuge nanoskalige Geräte Logic gates Layout Transistors Silicon Mathematical model Tools Nanoscale devices law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_INTEGRATEDCIRCUITS Silicon nanowires Lithography Electronic circuit 010302 applied physics Transistor Doping 020202 computer hardware & architecture chemistry CMOS Logic gate Routing (electronic design automation) Hardware_LOGICDESIGN |
| Zdroj: | DATE |
| Popis: | Silicon Nanowire (SiNW) based reconfigurable field-effect transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p-type or n-type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required, and no doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmarks. Further, we discuss areas of improvement for obtaining better area results from the SiNW based RFETs from a fabrication and technology point of view. The future use of self-aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction. |
| Databáze: | OpenAIRE |
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