Modified Predictive Direct Torque Control ASIC with Multistage Hysteresis and Fuzzy Controller for a Three-Phase Induction Motor Drive
| Autor: | Guo-Ming Sung, Li-Fen Tung, Chong-Cheng Huang, Hong-Yuan Huang |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
Computer Networks and Communications
Hardware and Architecture Control and Systems Engineering Signal Processing Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering induction motor predictive direct torque control (PDTC) fuzzy PID controller multistage hysteresis controller discrete multiple-voltage vector (DMVV) rounding-off calculation Verilog hardware description language (HDL) application-specific integrated circuit (ASIC) |
| Zdroj: | Electronics; Volume 11; Issue 11; Pages: 1802 |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics11111802 |
| Popis: | This paper proposes a modified predictive direct torque control (MPDTC) application-specific integrated circuit (ASIC) with multistage hysteresis and fuzzy controller to address the ripple problem of hysteresis controllers and to have a low power consumption chip. The proposed MPDTC ASIC calculates the stator’s magnetic flux and torque by detecting three-phase currents, three-phase voltages, and the rotor speed. Moreover, it eliminates large ripples in the torque and flux by passing through the modified discrete multiple-voltage vector (MDMVV), and four voltage vectors were obtained on the basis of the calculated flux and torque in a cycle. In addition, the speed error was converted into a torque command by using the fuzzy PID controller, and rounding-off calculation was employed to decrease the calculation error of the composite flux. The proposed MDMVV switching table provides 294 combined voltage vectors to the following inverter. The proposed MPDTC scheme generates four voltage vectors in a cycle that can quickly achieve DTC function. The Verilog hardware description language (HDL) was used to implement the hardware architecture, and an ASIC was fabricated with a TSMC 0.18 μm 1P6M CMOS process by using a cell-based design method. Measurement results revealed that the proposed MPDTC ASIC performed with operating frequency, sampling rate, and dead time of 10 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of the circuit were 2.457 mW and 1.193 mm × 1.190 mm, respectively. The proposed MPDTC ASIC occupied a smaller chip area and exhibited a lower power consumption than the conventional DTC system did in the adopted FPGA development board. The robustness and convenience of the proposed MPDTC ASIC are especially advantageous. |
| Databáze: | OpenAIRE |
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