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Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidance of over-constrained synchronization, and its simplified clocking requirements. However, analysis and optimization of self-timed systems under real-time constraints is challenging due to the complex, irregular dynamics of self-timed operation. This paper examines a number of intermediate representations for compiling data flow programs onto self-timed DSP platforms, and discusses efficient techniques that operate on these representations to streamline scheduling, communication synthesis, and power management of self-timed implementations. |
