Special session: Hot topics: Statistical test methods

Autor: Manuel J. Barragan, R.D. Blanton, Florence Azaïs, Adit D. Singh, Gildas Leger, Stephen Sunter
Přispěvatelé: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM CSIC), Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Spain] (CSIC), Seville Institute of Microelectronics (IMSE-CNM), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Carnegie Mellon University, Department of Engineering and Public Policy (CMU, EPP), Carnegie Mellon University [Pittsburgh] (CMU), Auburn University (AU), Mentor Graphics, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
Jazyk: angličtina
Rok vydání: 2015
Předmět:
Zdroj: 33rd IEEE VLSI Test Symposium
VTS: VLSI Test Symposium
VTS: VLSI Test Symposium, Apr 2015, Napa, CA, United States. ⟨10.1109/VTS.2015.7116265⟩
VTS
DOI: 10.1109/VTS.2015.7116265⟩
Popis: International audience; The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.Advanced statistical data processing offers a powerful set of tools, borrowed from the fields of data mining, machine learning or artificial intelligence, to get the most out of this data. Indeed, these mathematical tools have opened a number of novel and interesting research lines within the field of IC testing.In this special session, prominent researchers in this field will share their views on this topic and present some of their last findings. The first talk will discuss the interest of likelihood prevalence in random fault simulation. The second talk will show how statistical data analysis can help diagnosing test efficiency. The third talk will deal with the reliability of Alternate Test of AMS-RF circuits. The fourth and last talk will address the idea of mining the test data for improving design manufacturing and even test itself.
Databáze: OpenAIRE