Architectural improvements and technological enhancements for the APEnet+ interconnect system
| Autor: | Piero Vicini, Michele Martinelli, Davide Rossetti, Andrea Biagioni, Pierluigi Paolucci, F. Lo Cicero, Elena Pastorelli, Roberto Ammendola, Ottorino Frezza, Alessandro Lonardo, Laura Tosoratto, Francesco Simula |
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| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
FOS: Computer and information sciences
Network architecture Remote direct memory access Grid network business.industry Computer science Interface (computing) Electrical engineering FOS: Physical sciences Computational Physics (physics.comp-ph) Embedded system Hardware Architecture (cs.AR) Stratix Bandwidth (computing) business Field-programmable gate array Computer Science - Hardware Architecture Instrumentation Physics - Computational Physics Mathematical Physics PCI Express |
| Popis: | The APEnet+ board delivers a point-to-point, low-latency, 3D torus network interface card. In this paper we describe the latest generation of APEnet NIC, APEnet v5, integrated in a PCIe Gen3 board based on a state-of-the-art, 28 nm Altera Stratix V FPGA. The NIC features a network architecture designed following the Remote DMA paradigm and tailored to tightly bind the computing power of modern GPUs to the communication fabric. For the APEnet v5 board we show characterizing figures as achieved bandwidth and BER obtained by exploiting new high performance ALTERA transceivers and PCIe Gen3 compliancy. |
| Databáze: | OpenAIRE |
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