Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

Autor: Padmanabhan Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
Přispěvatelé: School of Computer Science and Engineering
Jazyk: angličtina
Rok vydání: 2020
Předmět:
Adder
Computer and Information Sciences
Computer science
Electrical Equipment and Supplies
Vector Spaces
Science
Materials Science
02 engineering and technology
Electronics Engineering
Micro-processing
Computer science and engineering::Hardware [Engineering]
0202 electrical engineering
electronic engineering
information engineering
Nanotechnology
Multiplication
Arithmetic
Materials
Digital signal processing
Multidisciplinary
Data Processing
business.industry
020208 electrical & electronic engineering
Nanoelectronics
Equipment Design
020202 computer hardware & architecture
Logic Circuits
Algebra
CMOS
Semiconductors
Linear Algebra
Asynchronous communication
Circuit Design
Physical Sciences
Engineering and Technology
Medicine
Multiplier (economics)
Electronics
business
Information Technology
Mathematics
Electrical Engineering
Research Article
Electrical Circuits
Zdroj: PLoS ONE, Vol 15, Iss 2, p e0228343 (2020)
PLoS ONE
ISSN: 1932-6203
Popis: Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology. Ministry of Education (MOE) Published version This work was supported by grants MOE2017-T2-1-002 and MOE2018-T2-2-024, Ministry of Education (MOE), Singapore.
Databáze: OpenAIRE
Externí odkaz:
Nepřihlášeným uživatelům se plný text nezobrazuje